In recent years, semiconductor process technology has rapidly progressed to permit increasingly complex systems both at the integrated-circuit level and at the circuit-board level. As a result, system designers have increased their demand for computer aided design ("CAD") tools to automate the design process and thereby reduce the time necessary to implement their system designs.
What was once a "bottom-up" design process, beginning from the circuit and gate level and working toward the system level, has become an increasingly "top-down" process, whereby the system designer designs a system at the abstract level and works down toward its implementation on the circuit and gate level.
A number of factors have been responsible for the move to a "top-down" approach. First, the availability of standard cell libraries, gate-arrays and ASIC ("Application Specific Integrated Circuit") technology has provided the system designer with a host of semiconductor building blocks with which to implement system designs. In addition, CAD tools are able to create hardware descriptions of systems designs using standard languages such as Verilog and VHDL ("Very High-Scale Integrated Circuit Hardware Description Language"). A system represented in VHDL can then be fed into a synthesis tool, which converts the VHDL representation into an actual circuit block implementation for a given semiconductor technology.
Before a system design is implemented, its behavior is typically verified in simulation. CAD tools simulate the system once it has been converted to a VHDL representation to verify logical behavior and/or timing behavior of the system. Some simulators are event-driven simulators while others are discrete time simulators.
Contention is a problem arising in an electronic circuit when more than one driver contends for utilization of a single bus. Contention is a serious design problem which should be detected in simulation to ensure that the resulting circuit operates as expected.
FIG. 1 depicts a typical simulated electronic circuit in which contention may arise. In FIG. 1, simulated drivers 100, 101 and 102 have their respective outputs 103, 104, and 105 interconnected to simulated bus 106. Each of these drivers can be either active or inactive. When inactive, the driver is in a high-impedance state and can be effectively considered to be disconnected from the bus. When active, the driver is driving the bus with a value of the active state. For example, in VHDL, the industry standard logic type has nine state values: 1, 0, H, L, -, Z, X, U, and W. Typically, 1, 0, -, X, U, and W are "active" state values while H, L, and Z are "inactive" state values. A contention condition will arise if more than one of these drivers provides an active output signal to the simulated bus during the same time interval. In conventional simulation systems, the bus is represented by an industry standard data type, such as the IEEE Std.sub.-- Logic. Associated with this data type is a resolution function. The input parameters to the resolution function are the output value of each driver connected to the bus. The resolution function then determines (or resolves) the value on the bus based upon these input parameters. The simulator invokes this resolution function during the simulation to determine the value on the bus. FIGS. 2A, 2B, and 2C illustrate a sample display of the values on a bus at different times by the simulator. FIGS. 2A and 2C illustrate a waveform representing a high (e.g., "1") and low (e.g., "0") value on the bus. When only one driver is active and outputting a high value the resolution function resolves to a bus value of high. When only one driver is active and outputting a low value the resolution function resolves to a bus value of low. If, however, multiple drivers are active and at least one driver is outputting a high value and at least one driver is outputting a low value, then the resolution function resolves to an indeterminate bus value as shown in FIG. 2B.
The conventional technique of detecting such contention during simulation requires visual inspection by a skilled technician of the waveforms representing the value on the simulated bus at various time intervals. That is, the technician would view the waveforms of FIGS. 2A and 2C and would note that the waveforms are normal, but when viewing the waveform of FIG. 2B, the technician would note that the waveform is abnormal. The technician may realize that the abnormality is a result of bus contention. Conventional techniques may display such abnormal waveforms in color to bring the abnormality to the attention of the technician.
Such bus contentions that result in the abnormal waveform occur when multiple drivers drive different active states. In other words, one driver provides an output such as that shown in FIG. 2A while another driver provides an output such as that shown in FIG. 2C. These contending outputs result in the signal on the bus going to the abnormal state which could be represented as shown in FIG. 2B or virtually any waveform other than the waveforms shown in FIG. 2A and FIG. 2C.
A problem arises in the conventional techniques because the output of the resolution function resolves to a normal value when more than one driver is active and the active drivers are outputting the same value. In other words, more than one driver is active on the bus but each of the drivers are outputting the same signal value, such as that shown in FIG. 2A or FIG. 2C. For example, drivers implemented with Gunning Transistor Logic "GTL" can only output one type of value when active. Thus, any time multiple GTL drivers are active the resolution function resolves to a normal value. Such an event does produce contention on the bus, but a contention condition arising in this manner will escape detection by the technician. The contention will be missed because the actual value of the signal on the bus resolves to a normal value. Thus, a visual inspection of the waveform would indicate that the value on the bus is normal.
An additional problem may also arise using the conventional techniques when contention only exists for a short duration (i.e., less than a clock cycle). The visual inspection technique may fail because the technician viewing the waveforms may have the display resolution of the simulation set at too coarse of a level to show the contention. The technique of detecting for the indeterminate state could fail because this technique normally only checks for indeterminate states at clock edges, since the contention is less than a clock cycle, it is not guaranteed to span a clock edge. The reason previous techniques only check for indeterminate states at clock edges is that normally simulation models drive indeterminate states as part of their normal operating procedures. For example, an "X" may be driven until the very end of the clock cycle before changing to a value such as "1". Simulations are typically driven in simulation time units which occur more frequently than a clock cycle. For example, a simulation time unit could represent a picosecond while a clock cycle occupies a nanosecond. In this example, the granularity of the simulation would be a picosecond. When driving a bus signal, a simulation model may bracket the data valid window (defined by bus specification) of that signal, such that, if the design under test does not meet timing, an indeterminate value is gated into the design, thereby, indicating an error condition.
One conventional technique for detecting contentions requires the use of external ports through which connections are added to the circuit design for examining the enable lines to the various drivers to detect when each of the drivers is in an active state. However, this conventional technique requires the simulated circuit to have additional connection points, connection points which would not be present in the circuit as implemented. In other words, such a simulation would test a circuit which is different from the circuit for which implementation is proposed.
Finally, another anomaly arises with conventional techniques caused because the initial state of the logic in most simulations is indeterminate. Thus, the conventional techniques suffer from an inability to distinguish between an initial state and an abnormal value caused by contention.